DireLeak: Cross-socket Cache Timing Channels Exploiting Memory Directory

Recommended citation: M. H. I. Chowdhuryy, K. Cai, Z. Zhang, H. Zheng, and F. Yao, “DireLeak: Cross-socket Cache Timing Channels Exploiting Memory Directory,” in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2026.